module tb;

   reg clock = 'b0;
   reg reset = 'b1;

   initial forever #5 clock = ~clock;
   initial #(5+100) reset = 'b0;
   
   ysyxSoCFull ldut ( // @[TestHarness.scala 15:19]
      .clock(clock),
      .reset(reset)
   );

   initial
      begin
         //$fdumpvars;
      end

endmodule

